A level shifting circuit is one with one portion of the circuit operating off one supply level while the other operates off a different supply level. An example of such a level switching circuit is one that links peripheral circuits which have a supply level of 1.8 volts to core circuits which operate at a 1.2 volts nominal. Therefore in this case, the front end of the receiver receives signals generated by circuits operating at the peripheral supply and provides outputs to circuits which operate with the core supply level which is lower than the peripheral supply level. Standard level shifters are very slow. This is because the capacitive loads of the CMOS devices in the receiving circuit are hard to shift from one operating state to another operating state but also to the systems that are the CMOS devices. As the operating speed of CMOS circuits has increased, the capacitive nature of the CMOS devices in the CMOS circuits has been an impediment to not only rapid operation of level shifting circuits. Further, most prior art level shifters provide an asymmetric output.
Therefore it is an object of the present invention to provide a higher speed level shifting circuit.
A further object of the invention is to provide a high speed level shifting circuit with an symmetric output.
Another object of the invention is to provide a circuit capable of switching large voltages rapidly.